1. Field of the Invention
The present invention relates to a technique for assisting in the design of a logic circuit, and particularly relates to a device and method for executing operational verification of the logic circuit.
2. Description of the Related Art
As the scale of circuits that can be mounted in digital LSI enlarges each year, the issue of increasing the speed of operational verification is becoming more and more important. Methods in general use for enhancing verification speed employ a hardware emulator that uses a programmable device such as FPGA (Field Programmable Gate Array) or CPLD (Complex Programmable Logic Device).
Japanese Laid-open Patent Application No. 2000-215226 discloses a logic verification device which can efficiently perform logic verification in the case where a module in which logic information is defined up to a structural level is mixed with a module in which such definition is not present. Specifically, the circuit being verified is divided into a first part verified by a hardware emulator and a second part verified by a software simulator depending on the level of abstraction of the logic information. The circuit verification is performed by synchronizing the clocks of the hardware emulator and the software simulator to perform mutual transfer of data (see paragraphs 0046 through 0052 and FIGS. 1 and 2). Since the logic being verified is executed not only by the software simulator but by the hardware emulator as well, verification can be performed at a higher speed than with a software simulator alone.
However, division of the circuit in the conventional logic verification device as described above is performed according to the level of abstraction of the logic information, so there is no degree of freedom in the circuit division, and an increase in the speed of verification cannot be achieved.
Furthermore, in the software simulator of the conventional logic verification device described above, data are sent and received to and from the hardware emulator via the CPU system bus, but the arrangement of the data that are sent and received follows the specifications of the system bus (see paragraph 0048 of Japanese Laid-open Patent Application No. 2000-215226). Because of this, the verification speed of the circuit is determined by the transfer speed of the bus, and efficient data transfer cannot be performed.